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DA9078.003 28 January 2004
MAS9078
AM Receiver IC
* * * * * * *
DESCRIPTION
The MAS9078 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. Unlike MAS1016A and MAS1016B, MAS9078 does not require AGC control procedure in WWVB and JJY systems.
High Sensitivity Very Low Power Consumption Wide Supply Voltage Range Power Down Control Control for AGC On High Selectivity by Crystal Filter Fast Startup Feature
FEATURES
* * * * * * * * * * Highly Sensitive AM Receiver, 0.4 VRMS typ. Wide Supply Voltage Range from 1.1 V to 3.6 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On Wide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter Die and TSSOP-16 Package
APPLICATIONS
* * Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany) and MSF (UK) Receiver for ASK Modulated Data Signals
BLOCK DIAGRAM
QO QI AON (=AGC on)
RFI
AGC Amplifier
Demodulator & Comparator
OUT
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC 1 (10)
DA9078.003 28 January 2004
PAD LAYOUT
1702 m
VSS RFI PDN AON DEC MAS
1778 m
9078Bx VDD QO QI AGC OUT
DIE size = 1.70 x 1.78 mm; PAD size = 100 x 100 m Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in the center of VDD pad Note: The on-chip product code 9078Bx identifies internal compensation capacitance option. x has values 1, 2, 3, 4 or 5 refering to capacitance option described in the Table 2 on page 4. Pin Description Power Supply Voltage Quarz Filter Output Quarz Filter Input AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Input Receiver Input Power Supply Ground Name VDD QO QI AGC OUT DEC AON PDN RFI VSS X-coordinate 0 m 306 m 586 m 866 m 1109 m 1109 m 866 m 549 m 306 m 16 m Y-coordinate 0 m 19 m 19 m 19 m 19 m 1428 m 1428 m 1428 m 1428 m 1407 m Note
1 2 3
Notes: 1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 A which is switched off at power down 3) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal.
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DA9078.003 28 January 2004
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD-VSS VIN PMAX TOP TST Conditions Min -0.3 VSS-0.3 -20 -40 Max 5.0 VDD+0.3 100 70 120 Unit V V mW o C o C
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25C
Parameter Operating Voltage Current Consumption Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Input Levels |lIN|<0.5 A Output Current VOL<0.2 VDD;VOH >0.8 VDD Output Pulse
Symbol VDD IDD IDDoff fIN VIN min VIN max VIL VIH |IOUT| T100ms T200ms T500ms T800ms
Conditions VDD=3.6 V, Vin=0 V VDD=1.4 V, Vin=0 V
Min 1.10 56
Typ 76 66
Max 3.60 95 0.1 100 1 0.2 VDD
Unit V A A kHz Vrms mVrms V A
40 0.4 20 0.8 VDD 5 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms Fast Start-up Without Fast Start-up 50 150 400 700 500 800 12 3 50
140 230 600 900
ms ms ms ms s min ms
Startup Time Output Delay Time
TStart TDelay
100
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DA9078.003 28 January 2004
TYPICAL APPLICATION
Note 1
X1 QO FerriteAntenna RFI AGC Amplifier QI
AON (=AGC on)
Demodulator & Comparator
OUT
Receiver output
VDD 1.4 V
Power Supply/Biasing VSS PDN Note 2 CAGC 10 uF CDEM 47 nF AGC DEC
Note 3 Power Down / Fast Startup Control
Note 1: Crystal The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance compensation capacitance CC. MAS9078 has five compensation capacitance options. Capacitance values and suitable crystals are described in Table 2. See also Ordering Information (p.10). Time-Signal System DCF77 MSF WWVB JJY Table 1 Device MAS9078B1 MAS9078B2 MAS9078B3 MAS9078B4 MAS9078B5 Table 2 Location Antenna Frequency Recommended Crystal Frequency 77.503 kHz 60.003 kHz 60.003 kHz 40.003 kHz and 60.003 kHz
Germany 77.5 kHz United Kingdom 60 kHz USA 60 kHz Japan 40 kHz and 60 kHz Time-Signal System Frequencies CC Crystal Description
0.75 pF For single low C0 crystal (Nominal value) 1.25 pF For single high C0 crystal 1.625 pF For two parallel low C0 crystals (dual band receiver) 2.5 pF For two parallel high C0 crystals (dual band receiver) 3.875 pF Any crystal with parallel external compensation capacitor Compensation Capacitance Options
Note 2: AGC Capacitor The AGC and DEC capacitors must have low leakage currents due to very small 40 nA signal currents through the capacitors. The insulation resistance of these capacitors should be higher than 70 M. Also probes with at least 100 M impedance should be used for voltage probing of AGC and DEC pins. Note 3: Power Down / Fast Startup Control Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered by the falling edge of PDN signal, i.e., controlling device from power down to power up. The startup time without using the fast startup control can be several minutes but with fast startup it is shortened typically to 12 s.
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DA9078.003 28 January 2004
SAMPLES IN SBDIL 20 PACKAGE
NC
1
VDD 2 NC 3 QO 4 NC 5 QI 6 AGC 7 OUT 8 NC 9 NC 10
MAS9078 YYWW XXXXX.X
20 VSS 19 NC 18 RFI 17 PDN 16 AON 15 DEC 14 NC 13 NC 12 NC 11 NC Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number
PIN DESCRIPTION
Pin Name NC VDD NC QO NC QI AGC OUT NC NC NC NC NC NC DEC AON PDN RFI NC VSS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type P AO AI AO DO Function Positive Power Supply Quartz Filter Output 1 Quartz Filter Input AGC Capacitor Receiver Output Note
2
AO DI AI AI
Demodulator Capacitor AGC On Control Power Down Input Receiver Input
3 4
G Power Supply Ground Notes: 1) Pin 5 between quartz crystal filter pins must be connected to VSS to eliminate DIL package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 A which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal.
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DA9078.003 28 January 2004
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VDD NC QO NC QI AGC NC OUT
VSS NC RFI NC PDN AON NC DEC
YYWW
9078
Top Marking Definitions: YYWW = Year Week
PIN DESCRIPTION
Pin Name VDD NC QO NC QI AGC NC OUT DEC NC AON PDN NC RFI NC VSS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type P AO AI AO DO AO DI AI AI G Function Positive Power Supply Quartz Filter Output 1 Quartz Filter Input AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Input Receiver Input Power Supply Ground 2 Note
3 4
Notes: 1) Pin 4 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up (to AGC on) with current < 1 A which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal.
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DA9078.003 28 January 2004
PACKAGE (TSSOP16) OUTLINES
C
D Seating Plane B A F G H
E
O Pin 1 Detail A
B B
L I I1 K P Section B-B J1 J M N
Detail A
Dimension A B C D E F G H I I1 J J1 K L M (The length of a terminal for soldering to a substrate) N O P
Min 6.40 BSC 4.30 5.00 BSC 0.05 0.19 0.65 BSC 0.18 0.09 0.09 0.19 0.19 0 0.24 0.50 1.00 REF 12 12
Max 4.50 0.15 1.10 0.30 0.28 0.20 0.16 0.30 0.25 8 0.26 0.75
Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm
Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153.
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DA9078.003 28 January 2004
SOLDERING INFORMATION
Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile Seating Plane Co-planarity Lead Finish According to RSH test IEC 68-2-58/20 2*220C 240C 2 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 m, material Sn 85% Pb 15%
EMBOSSED TAPE SPECIFICATIONS
Tape Feed Direction P0 D0 P2
A E1 F1 W
D1 A P A0 Tape Feed Direction T Section A - A B0 S1 K0
Dimension A0 B0 D0 D1 E1 F1 K0 P P0 P2 S1 T W Min 6.50 5.20 1.50 +0.10 / -0.00 1.50 1.65 7.20 1.20 11.90 4.0 1.95 0.6 0.25 11.70 2.05 0.35 12.30 1.85 7.30 1.40 12.10
Pin 1 Designator
Max 6.70 5.40 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm
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DA9078.003 28 January 2004
REEL SPECIFICATIONS
W2
A
D B
Tape Slot for Tape Start
C
N
W1
2000 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape
Cover Tape End
Start
Trailer
Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Min
Components
Max 330 1.5 12.80 20.2 50 12.4 13.50 14.4 18.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape 1500
Leader
Unit mm mm mm mm mm mm mm mm mm
Weight
g
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DA9078.003 28 January 2004
ORDERING INFORMATION
Product Code MAS9078BTB1 MAS9078BTB2 MAS9078BTB3 MAS9078BTB4 MAS9078BTB5 MAS9078BTC1 MAS9078BTC2 MAS9078BTC3 MAS9078BTC4 MAS9078BTC5 MAS9078BUA1-T Product AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC AM-Receiver IC Package EWS-tested wafer, Thickness 480 m EWS-tested wafer, Thickness 480 m EWS-tested wafer, Thickness 480 m EWS-tested wafer, Thickness 480 m EWS-tested wafer, Thickness 480 m EWS-tested wafer, Thickness 400 m EWS-tested wafer, Thickness 400 m EWS-tested wafer, Thickness 400 m EWS-tested wafer, Thickness 400 m EWS-tested wafer, Thickness 400 m TSSOP-16, Tape & Reel Capacitance Option CC = 0.75 pF (Nominal) CC = 1.25 pF CC = 1.625 pF CC = 2.5 pF CC = 3.875 pF CC = 0.75 pF CC = 1.25 pF CC = 1.625 pF CC = 2.5 pF CC = 3.875 pF CC = 0.75 pF (Nominal)
Contact Micro Analog Systems Oy for other wafer thickness options.
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
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